The present invention relates generally to methods of thin film deposition and, particularly, to a process of filling high aspect ratio gaps on substrates using high density plasma (HDP) chemical vapor deposition (CVD).
As semiconductor technology advances, circuit elements and interconnections on wafers or silicon substrates become increasingly more dense. In order to prevent unwanted interactions between these circuit elements, insulator-filled gaps or trenches located therebetween are provided to physically and electrically isolate the elements and conductive lines. However, as circuit densities continue to increase, the widths of these gaps decrease, thereby increasing gap aspect ratios, typically defined as the gap height divided by the gap width. As a result, filling these narrower gaps becomes more difficult, which can lead to unwanted voids and discontinuities in the insulating or gap-fill material.
Currently, high density plasma (HDP) oxide deposition is used to fill high aspect ratio gaps. Typical HDP deposition processes employ chemical vapor deposition (CVD) with a gas mixture containing oxygen, silane, and argon to achieve simultaneous dielectric etching and deposition. In an HDP process, an RF bias is applied to a wafer substrate in a reaction chamber. Some of the gas molecules (particularly argon) in this gas mixture are ionized in the plasma and accelerate toward the wafer surface when the RF bias is applied to the substrate. Material is thereby sputtered when the ions strike the surface. As a result, dielectric material deposited on the wafer surface is simultaneously sputter-etched to help keep gaps open during the deposition process, which allows higher gap aspect ratios to be filled.
FIGS. 1A-1D illustrate, in more detail, the simultaneous etch and deposition (etch/dep) process described above. In FIG. 1A, SiO2, formed from silane (SiH4) and oxygen (O2), begins depositing on the surface of a wafer 100 for filling a gap 110 between circuit elements 120. As the SiO2 is being deposited, charged ions impinge on the SiO2 or dielectric layer 125, thereby simultaneously etching the SiO2 layer. However, because the etch rate at about 45xc2x0 is approximately three to four times the etch rate on the horizontal surface, 45xc2x0 facets 130 form at the corners of elements 120 during the deposition process, as shown in FIG. 1B. FIGS. 1C and 1D show the process continuing to fill gap 110 with simultaneous etching and deposition of SiO2.
In FIGS. 1A-1D, the etch/dep ratio is optimized such that facets 130 remain at the corners of circuit elements 120 throughout the HDP deposition process. However, as shown in FIG. 2A, if the etch/dep ratio is decreased, facets 130 begin moving away from the corners of elements 120, and cusps 210 begin to form on sidewalls of gap 110. Cusp formation is due to some of the etched SiO2 being redeposited on opposing surfaces through line-of-sight redeposition, even though most of the etched SiO2 is emitted back into the plasma and pumped out of the reaction chamber. This redeposition increases as the distance between opposing surfaces decreases. Therefore, as facets 130 move away from the corners of elements 120, the line-of-sight paths are shortened, resulting in increased sidewall redeposition. At a certain point in the process, cusps 210 will meet and prevent further deposition below the cusps. When this occurs, a void 220 is created in dielectric layer 125, as shown in FIG. 2B. On the other hand, if the etch/dep ratio is increased, as shown in FIG. 3, the etching component can etch or xe2x80x9cclipxe2x80x9d material from the corners of elements 120, thereby damaging elements 120 and introducing etched contaminants 310 into dielectric layer 125.
The etch/dep ratio can be controlled by varying the flow rate of silane or other process gases, which affect the deposition rate, or by varying either the power supplied to the wafer for biasing or the flow rate of argon, which affect the sputter etch rate. Etch rates are typically increased by increasing the flow rate of argon, which is used solely to promote sputtering, rather than increasing power and expending large amounts of energy. Typical argon flow rates for HDP deposition range from 30%-60% or more of the total process gas flow rate. By optimizing the etch/dep ratio, gaps with aspect ratios of up to about 3.0:1 can be filled without void formation. However, as shown in FIG. 4, filling higher gap aspect ratios results in voids 410 due to cusps 420 prematurely closing the gaps even if the etch/dep ratio is optimized to 1 at the element corners. As discussed above, this is due mainly to the shortened line-of-sight path between opposing sidewalls. If the etch rate is increased to keep the gaps open longer, undesirable corner clipping can occur.
Therefore, with increasing circuit densities, higher gap aspect ratios need to be filled without the problems discussed above with current HDP deposition processes.
In accordance with the present invention, a high aspect ratio gap-fill process uses high density plasma (HDP) deposition processes with helium or other inefficient sputtering inert gases instead of argon to reduce the effects of sputtering and redeposition. In some embodiments, argon can be eliminated. Because the sputtering agent is greatly reduced, the etch or sputter rate decreases and the facet moves away from the element corners, as expected. However, cusps do not form on the element sidewalls because much less material is etched and available for redeposition. Consequently, with a greatly reduced sputter component, gaps remain open longer so that higher aspect ratio gaps can be filled without the formation of voids.
Because oxygen also contributes to the sputtering component, reducing the partial pressure of oxygen further reduces the sputtering and redeposition effect and allows increased gap-fill capabilities. However, in order to preserve the stoichiometry of the film, the partial pressure of silane (SiH4) is decreased as well. Helium, which is an inefficient sputtering agent, can be added to maintain a constant overall process gas flow rate and provide a constant uniform deposition rate across the wafer.
The present invention will be better understood in light of the following detailed description, taken together with the accompanying drawings.